1. Technical Field
The embodiments described herein relate to a semiconductor memory apparatus and, more particularly, to a semiconductor memory apparatus capable of increasing an area margin.
2. Related Art
A conventional DRAM (Dynamic Random Access Memory) stores data through a plurality of memory cells, each of which includes one transistor and one capacitor. Each memory cell is coupled to a word line and bit lines. The word line is coupled to a sub-word line driver and the bit lines are coupled to a bit line sense amplifier.
The bit lines are grouped into pairs and data is loaded on to pairs of bit lines. The data loaded on a pair of the bit lines have opposite phases with each other. Each pair of bit lines is coupled to a pair of sub-local data buses and the sub-local data buses are coupled to a pair of local data lines. Data bus switches are disposed between a pair of local data buses and a pair of the sub-local data buses. Each pair of local data buses communicates with a global data bus through a data I/O (input/output) sense amplifier.
A memory cell region can be defined by a set of memory cells coupled to the pair of the sub-local data buses, which is a minimum unit area which is defined by dividing a memory block having a plurality of memory cells based on the pair of the sub-local data buses and the pair of the local data buses. A memory bank is then constructed from associated a plurality of the sub-local data buses, the local data buses and the memory cell regions.
FIG. 1 is a block diagram illustrating a conventional semiconductor memory apparatus. More specifically, a memory block that includes a plurality of memory cell regions 10 is shown in FIG. 1. Particularly, sixteen memory cell regions are exemplarily shown in FIG. 1.
As shown in FIG. 1, the memory block of the conventional semiconductor memory apparatus includes memory cell regions 10, sub-local data buses 1, local data buses 2a to 2d, data bus switches 3 and data I/O sense amplifiers 20a to 20d. 
The sub-local data buses 1 perform data I/O operations within the memory cell regions 10. The local data buses 2a to 2d perform data I/O operations with the sub-local data buses 1. The data bus switches 3 are disposed between the sub-local data buses 1 and the local data buses 2a to 2d to selectively switch between these bus lines. The data I/O sense amplifiers 20a to 20d amplify data transmitted from the local data buses 2a to 2d. 
Still referring to FIG. 1, each sub-local data bus 1 is composed of a pair of a positive line and a negative line. Each of the local data buses 2a to 2d are also composed of a positive line and a negative line. AS can be seen, the sub-local data buses 1 and the local data buses cross each other at the upper right hand corners of the memory cell regions 10.
Insulating regions 4 are provided between the sub-local data buses 1 so that a data transmission region is defined within the memory block. Each of the sub-local data buses 1 can perform data I/O operations for two memory cell regions 10. The data bus switches 3 selectively connect the sub-local data buses 1 to the local data buses 2a to 2d in response to address signals. As can be seen, each local data bus line 2a to 2d can be configured to perform data I/O operations for 4 memory cell regions 10. Each of the local data buses 2a to 2d is then coupled to one of the data I/O sense amplifiers 20a to 20d. 
Referring to FIG. 2, a bit line sense amplifier block 30 and a sub-word line driver block 40 are arranged on the outskirts of the memory cell region 10. Sub-word line drivers (not shown) provided in the sub-word line driver block 40 carry out a function of reinforcing voltages applied to the plurality of word lines in the memory cell region 10. The bit line sense amplifier block 30, which is also coupled to the memory cell region 10, amplifies I/O data on bit lines (not shown) disposed between the memory cell region 10 and the sub-local data buses 1. Again, as can be seen, the associated sub-local data bus pair 1 is coupled to the local data bus pair 2a. 
As integration increases, the space allocated for each memory cell region is reduced, and it is becoming increasingly difficult to ensure a sufficient area margin using conventional fabrication techniques and circuit designs.